1. Field of the Invention
The present invention relates to the simulation method of a large-scale logical circuit, and more particularly to a distribution type super-parallel processor method cycle-based logical simulation device for executing the high-speed simulation of a large-scale digital circuit with several ten million or more gates at a logical block level.
2. Description of the Related Art
Recently, with the rapid progress of a complementary metal-oxide semiconductor large-scale integration (CMOS LSI) technology, the improvement in performance and function of digital system equipment has been promoted. How early high-quality design is realized and a new product is marketed in a state where the reduction of a product development period is promoted is the most important problem in new product development. To solve this problem, a large-capacity and high-speed simulation device for efficiently performing the logical verification of a large-scale system circuit is strongly demanded.
In such a situation, exclusive hardware has been studied and developed in order to improve logical simulation performance. These exclusive hardware realizing methods are basically classified into a processor method and a field programmable gate array (FPGA) method.
In the processor method, a circuit model is converted into a processor instruction and a simulation algorithm is executed. Compared with the FPGA method for simulating an actual hardware circuit, although its process speed is low, the set-up time of the circuit model is short. Therefore, by increasing the number of processors, its performance can be improved and its capacity can be increased.
In the FPGA method, since a circuit operation can be directly simulated by mapping a circuit model, high-speed processing can be realized. However, it is difficult to increase capacity for the reason that the number of operating frequencies decreases as circuit scale increases.
Basically processor method simulation-exclusive hardware is largely classified into a level sort method and an event method.
In the level sort method, a level number is assigned according to the number of steps after the external input terminal or storage device of a circuit to which logical verification is applied, and simulation is sequentially executed according to the level number. By executing simulation, calculation is conducted for all gates, regardless of the change in output of a gate corresponding to this level number.
In the event method, the output of a gate is evaluated in accordance with the event, event-driven, that is, by using the change of an input signal as event. If the output changes, the change is propagated in the circuit as event, and gate calculation is sequentially made.
Exclusive hardware for executing simulation at a logical block level, based on an algorithm obtained by combining the level sort method and level method is announced. However, the present invention targets a logical simulation device adopting the level sort method. Since any exclusive hardware based on such a level sort method cannot handle delay time, this is a cycle-based type simulator targeting a synchronous circuit.
Concerning the above-mentioned logical simulation device and a super-parallel processor combination method, there are the following reference literatures.
Patent Reference 1:
Japanese Patent Application No. 2000-36737 “Method Using Electrically Re-configurable Gate Array Logical and Device Configured by it”
Patent Reference 2:
Japanese Patent Application No. H7-200508 “Inter-node Combination Method”
Patent Reference 3:
Japanese Patent Application No. S64-26969 “Programmable Accelerator and Method thereof”
Patent reference 1 discloses a system suitable for a variety of objects including simulation, prototyping and an implementation plan, in which electrically re-configurable gate arrays are re-configurably connected to each other, a digital circuit network realized on a reciprocally connected chip by connection re-configuration.
Patent reference 2 discloses a combination method in which a second type node is connected in a specific dimension to first type nodes connected by links in the shape of n-dimensional mesh as combination topology for super-parallel computers.
Patent reference 3 discloses a programmable accelerator that is, a programmable logical simulation device, in which a plurality of substantially the same type processor elements are flexibly connected to each other via switch in such away as to form a cluster, and the processors are programmable.
In the above-mentioned simulation hardware or reference literatures, even if the level sort method targeted by the present invention is used, simulation is executed at a gate level, and a logical simulation device for executing simulation at a logical block level is not realized.
Although the level sort method is theoretically used from the oldest time, as described above, the calculation of all gates is needed at each level. Therefore, the amount of calculation becomes very large, and it is considered to be difficult to manufacture a device of a practically usable scale in order to apply it to the logical simulation of a large-scale digital circuit composed of several ten million or more gates.
Next, in the conventional logical simulator, generally a processor for calculation, that is, evaluation and a processor for communication between processors are separated. Specifically, a processor group for parallel processing and a communication network are separated. Since each communication distance between processors is different, the speed of the entire system degrades.
FIGS. 14 and 15 explain this problem. FIG. 14 shows the configuration of the conventional logical simulation device, in which a processor group and a network are separated.
Simulation includes logical operation, that is, evaluation and update work accompanying the evaluation. In order to realize a high-speed process, evaluation is divided and is performed in parallel. As to the update of the result, since processors are distributed as an evaluation unit for using an evaluation result, a network for a propagation process is needed to notify the other processors of the result.
Specifically, after the evaluation result of each processor is propagated to a processor needing the result, a subsequent operation is started. In this case, the performance of the system depends on two factors of evaluation speed and propagation speed. If the propagation speed is low, the speed of the system degrades as a whole.
FIG. 15 shows the propagation of an evaluation result between processors. In this example, it is assumed that the evaluation result of a processor 0 (PE0) must be propagated to a nearby PE1 and a remote PEn. In the conventional method, the propagation speed of the entire system depends on time needed to propagate the evaluation result to the remote processor PEn. Conventionally, this propagation time problem has been coped with by reducing the influence of this propagation time utilizing pipeline processing, overlapping processing and the like. However, if the number of processors must be widely increased in order to perform a large-scale data process, it is becoming difficult to improve propagation speed because of the physical restriction of hardware.